Implement F= not (AB+CD) using CMOS gates?

1 Answers   Intel,

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How do you detect a sequence of "1101" arriving serially from a signal line?

7 Answers   nvidia,

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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What is Cross Talk?

4 Answers   Intel,

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What does the above code synthesize to?

0 Answers   Intel,

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What are the limitations in increasing the power supply to reduce delay?

2 Answers   Infosys,

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What?s the critical path in a SRAM?

2 Answers   Infosys, Intel, Texas,

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What are the changes that are provided to meet design power targets?

0 Answers  

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Explain what is the depletion region?

0 Answers  

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Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

0 Answers   Infosys,

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Design an 8 is to 3 encoder using 4 is to encoder?

0 Answers   Intel,

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Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

3 Answers   Intel,

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