What are the changes that are provided to meet design power targets?

0 Answers  

---

Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

0 Answers   Infosys,

---

What is setup time and hold time?

1 Answers   Intel,

---

Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?

13 Answers   Intel,

---

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.

0 Answers   Infosys,

---

What?s the critical path in a SRAM?

2 Answers   Infosys, Intel, Texas,

---

In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

1 Answers   Intel,

---

Are you familiar with VHDL and/or Verilog?

17 Answers   Intel,

---

Explain the Various steps in Synthesis?

0 Answers   Intel,

---

Insights of a Tri-state inverter?

1 Answers   Intel,

---

What is Noise Margin? Explain the procedure to determine Noise Margin?

0 Answers  

---

Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

3 Answers   Intel,

---