Answer / Ranjan Pandey

Factors affecting power consumption on a chip include clock frequency, supply voltage, transistor switching activity, and circuit design complexity. Techniques to reduce power consumption include dynamic power management, low-power design methodologies, and low-voltage design techniques.

Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

1 Answers   Infosys,

---

Explain the three regions of operation of a mosfet.

1 Answers  

---

Give various factors on which threshold voltage depends.

1 Answers  

---

What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

0 Answers   Intel,

---

In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

3 Answers   IBM, Intel, nvidia,

---

What is interrupt latency?

3 Answers  

---

What are the steps involved in preventing the metastability?

1 Answers  

---

What is the main function of metastability in vsdl?

1 Answers  

---

What transistor level design tools are you proficient with? What types of designs were they used on?

1 Answers   Intel,

---

What is latchup? Explain the methods used to prevent it?

2 Answers   Intel,

---

Are you familiar with the term snooping?

1 Answers   Intel,

---

Explain what is multiplexer?

1 Answers  

---