Interested to Buy Any Domain ? << Click Here >> for more details...
Explain ASIC Design Flow?
- 2 Answers
- 15428 Views
- Intel, JK Associates, Mind Tree, I also Faced
- E-Mail Answers
Answer Posted / david schkolnik
To Answer #1 I must add the check done between steps:
After:
architecture is defined: Review with peers:
RTL coding: Logic simulation with tools like NCsim
Synthesis: first shot STA of (with estimated delays).
Formal verification against RTL (w/Formality)
DFT insertion and ATPG: Logic simulation, coverage, - Formal verification against
pre-DFT netlist.
Place and Route: sign-off STA (with actual delays)
LVS, DRC
Because the Verification process of the original code continues in parallel during the rest of the project, some bugs come up very late when it's too late to re-do the whole thing. Sometimes timing problems need late fixes. These small changes are called ECO, which are made straight on Layout. Then LVS needs to be run again and the result be analyzed by the top engineers in the team. Still, many bugs are born in this stage.
| Is This Answer Correct ? | 2 Yes | 2 No |
Post New Answer View All Answers
why is the number of gate inputs to CMOS gates usually limited to four?
Insights of a 4bit adder/Sub Circuit?
Working of a 2-stage OPAMP?
What was your role in the silicon evaluation/product ramp? What tools did you use?
Explain what is the use of defpararm?
Cross section of a PMOS transistor?
What is the ideal input and output resistance of a current source?
What happens if we delay the enabling of Clock signal?
Are you familiar with the term snooping?
Draw a CMOS Inverter. Explain its transfer characteristics
Mention what are the different gates where Boolean logic are applicable?
How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
Give various factors on which threshold voltage depends.
Explain the working of Insights of a pass gate ?
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
