Explain ASIC Design Flow?
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Answer Posted / david schkolnik
To Answer #1 I must add the check done between steps:
After:
architecture is defined: Review with peers:
RTL coding: Logic simulation with tools like NCsim
Synthesis: first shot STA of (with estimated delays).
Formal verification against RTL (w/Formality)
DFT insertion and ATPG: Logic simulation, coverage, - Formal verification against
pre-DFT netlist.
Place and Route: sign-off STA (with actual delays)
LVS, DRC
Because the Verification process of the original code continues in parallel during the rest of the project, some bugs come up very late when it's too late to re-do the whole thing. Sometimes timing problems need late fixes. These small changes are called ECO, which are made straight on Layout. Then LVS needs to be run again and the result be analyzed by the top engineers in the team. Still, many bugs are born in this stage.
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