Are you familiar with the term MESI?
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Why do we need both PMOS and NMOS transistors to implement a pass gate?
What was your role in the silicon evaluation/product ramp? What tools did you use?
what is multiplexer?
How to find the read failiure probablity in SRAM?
Explain the difference between write through and write back cache.
What transistor level design tools are you proficient with? What types of designs were they used on?
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop?
What are the ways to Optimize the Performance of a Difference Amplifier?
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?