Explain the operation of a 6T-SRAM cell?

0 Answers   Intel,

---

How logical gates are controlled by boolean logic?

0 Answers  

---

Give the cross-sectional diagram of the cmos.

0 Answers  

---

Explain Basic Stuff related to Perl?

0 Answers   Intel,

---

what is Latch up?How to avoid Latch up?

3 Answers  

---

For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

0 Answers   Intel,

---

What happens to delay if we include a resistance at the output of a CMOS circuit?

1 Answers   Infosys,

---

For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

0 Answers   Infosys,

---

Who provides the DRC rules?

5 Answers   Intel,

---

For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

0 Answers   Infosys,

---

Explain the working of Insights of an inverter ?

0 Answers   Intel,

---

Explain what is the depletion region?

0 Answers  

---