Answer / Sandeep Kumar Singh

Synchronous reset requires a clock signal to propagate the reset, while asynchronous reset does not. Asynchronous resets can change the state of the circuit immediately, but are more prone to glitches and race conditions.

What is FPGA?

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Explain the three regions of operation of a mosfet.

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If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

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What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

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Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

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What are the ways to Optimize the Performance of a Difference Amplifier?

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Draw the stick diagram of a NOR gate. Optimize it

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In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

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What is clock feed through?

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How logical gates are controlled by boolean logic?

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What types of high speed CMOS circuits have you designed?

2 Answers   Infosys, Intel,

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