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Explain about stuck at fault models, scan design, BIST and
IDDQ testing?
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Answer / navya
IDDQ testing:usually performed at the beginning of test cycle.The test checks for leakage current to know if it is in normal range or abnormal range.If abnormal die fails,it is rejected and no further tests are performed.Iddq testing can detect clusters of gate oxide shorts(GOS) where gate voltage has no control over drain current and they tend to increase leakage levels.
BIST(built in self test): used to meet requirements such as high reliability and low repair cycle times.Bist reduces need for external testing(ATE).But the disadvantage is additional silicon area needed to implement BIST circuitry.
Scan design:test methodology built into digital chips
All flipflop are provided with alternate i/p for data as well as a separate clk i/p for scan testing.F/f connected together in scan chains.Testing is done by entering a special test mode called "scan mode" where test vectors is i/p to each scan chain and the bits clkd through all f/f's in the chain with resulting o/p chkd for errors.
Stuck at fault models:
stuck-on fault:always conducts Ids with an applied Vds,gate has no control over the operation
stuck off faults:current never flows regardless of Vgs or Vds.
| Is This Answer Correct ? | 13 Yes | 1 No |
Answer / seetharamukg
IDDQ testing is used for testing the library cells. Meaning
if any faults are there in our design we are going for DFT.
If any faults are there in the library itself we are doing
IDDQ testing.
| Is This Answer Correct ? | 3 Yes | 9 No |
Answer / shashank parashar
BIST is a biult in self test,in which we are going to test
our circuit in chip only.
Dft is a design for test.
IDDQ testing is used for testing the library cells.
| Is This Answer Correct ? | 3 Yes | 9 No |
Implement a 2 I/P and gate using Tran gates?
Need to convert this VHDL code into VLSI verilog code? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of specific package--- ENTITY tollbooth2 IS PORT (Clock,car_s,RE : IN STD_LOGIC; coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); r_light,g_light,alarm : OUT STD_LOGIC); END tollbooth2; ARCHITECTURE Behav OF tollbooth2 IS TYPE state_type IS (NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE D); ------GOTZERO = PAID $0.00--------- ------GOTFIV = PAID $0.05---------- ------GOTTEN = PAID $0.10---------- ------GOTFIF = PAID $0.15---------- ------GOTTWEN = PAID $0.20--------- SIGNAL present_state,next_state : state_type; BEGIN -----Next state is identified using present state,car & coin sensors------ PROCESS(present_state,car_s,coin_s) BEGIN CASE present_state IS WHEN NO_CAR => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= NO_CAR; END IF; WHEN GOTZERO => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTZERO; ELSIF (coin_s = "01") THEN next_state <= GOTFIV; ELSIF (coin_s ="10") THEN next_state <= GOTTEN; END IF; WHEN GOTFIV=> IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIV; ELSIF (coin_s = "01") THEN next_state <= GOTTEN; ELSIF (coin_s <= "10") THEN next_state <= GOTFIV; END IF; WHEN GOTTEN => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s ="00") THEN next_state <= GOTTEN; ELSIF (coin_s="01") THEN next_state <= GOTFIV; ELSIF (coin_s="10") THEN next_state <= GOTTWEN; END IF; WHEN GOTFIF => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIF; ELSIF (coin_s ="01") THEN next_state <= GOTTWEN; ELSIF (coin_s = "10") THEN next_state <= GOTTWEN; END IF; WHEN GOTTWEN => next_state <= CAR_PAID; WHEN CAR_PAID => IF (car_s = '0') THEN next_state <= NO_CAR; ELSE next_state<= CAR_PAID; END IF; WHEN CHEATED => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= CHEATED; END IF; END CASE; END PROCESS;-----End of Process 1 -------PROCESS 2 for STATE REGISTER CLOCKING-------- PROCESS(Clock,RE) BEGIN IF RE = '1' THEN present_state <= GOTZERO; ----When the clock changes from low to high,the state of the system ----stored in next_state becomes the present state----- ELSIF Clock'EVENT AND Clock ='1' THEN present_state <= next_state; END IF; END PROCESS;-----End of Process 2------- --------------------------------------------------------- -----Conditional signal assignment statements---------- r_light <= '0' WHEN present_state = CAR_PAID ELSE '1'; g_light <= '1' WHEN present_state = CAR_PAID ELSE '0'; alarm <= '1' WHEN present_state = CHEATED ELSE '0'; END Behav;
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