Explain the operation of a 6T-SRAM cell?

0 Answers   Intel,

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How can you model a SRAM at RTL Level?

0 Answers   Infosys,

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Why don?t we use just one NMOS or PMOS transistor as a transmission gate?

2 Answers   Infosys,

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How do you size NMOS and PMOS transistors to increase the threshold voltage?

4 Answers  

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What are the different limitations in increasing the power supply to reduce delay?

2 Answers  

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Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

0 Answers   Infosys,

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Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

0 Answers   Infosys,

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You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

4 Answers   Intel,

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How to find the read failiure probablity in SRAM?

2 Answers  

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Explain why present VLSI circuits use MOSFETs instead of BJTs?

0 Answers  

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What is a linked list? Explain the 2 fields in a linked list?

1 Answers   Intel,

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Explain about stuck at fault models, scan design, BIST and IDDQ testing?

3 Answers   Intel,

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