What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

0 Answers   Intel,

---

Explain the Charge Sharing problem while sampling data from a Bus?

1 Answers  

---

What are the main issues associated with multiprocessor caches and how might you solve them?

0 Answers   Intel,

---

While using logic design, explain the various steps that r followed to obtain the desirable design in a well defined manner?

1 Answers   Intel,

---

Draw a 6-T SRAM Cell and explain the Read and Write operations

0 Answers   Infosys,

---

what is short Channel effect.

2 Answers  

---

Give the various techniques you know to minimize power consumption?

5 Answers  

---

Why do we need both PMOS and NMOS transistors to implement a pass gate?

3 Answers   INEL, Intel,

---

What happens to delay if you increase load capacitance?

3 Answers   Infosys,

---

Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

---

Differences between blocking and Non-blocking statements in Verilog?

5 Answers   Intel,

---

Explain what is the depletion region?

0 Answers  

---