Explain about stuck at fault models, scan design, BIST and
IDDQ testing?
- 3 Answers
- 12051 Views
- Intel, I also Faced
- E-Mail Answers
Answer Posted / shashank parashar
BIST is a biult in self test,in which we are going to test
our circuit in chip only.
Dft is a design for test.
IDDQ testing is used for testing the library cells.
| Is This Answer Correct ? | 3 Yes | 9 No |
Post New Answer View All Answers
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
Mention what are the two types of procedural blocks in Verilog?
What are the Factors affecting Power Consumption on a chip?
Explain the Various steps in Synthesis?
Explain the three regions of operation of a mosfet.
What types of CMOS memories have you designed? What were their size? Speed?
Explain how binary number can give a signal or convert into a digital signal?
Implement a 2 I/P and gate using Tran gates?
Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
Write a VLSI program that implements a toll booth controller?
For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
What is the ideal input and output resistance of a current source?
Explain the working of 4-bit Up/down Counter?
