Explain CMOS Inverter transfer characteristics?

0 Answers   ADS,

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How can you model a SRAM at RTL Level?

0 Answers   Infosys,

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What are the different design constraints occur in the synthesis phase?

0 Answers  

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In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

0 Answers  

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In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?

0 Answers  

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what is short Channel effect.

2 Answers  

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What is setup time and hold time?

1 Answers   Intel,

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For f = AB+CD if B is S-a-1, what r the test vectors needed to detect the fault?

5 Answers   Intel,

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Give the expression for calculating Delay in CMOS circuit?

1 Answers   Infosys,

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How can you model a SRAM at RTL Level?

1 Answers  

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What?s the critical path in a SRAM?

2 Answers   Infosys, Intel, Texas,

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You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

0 Answers   Intel,

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