Interested to Buy Any Domain ? << Click Here >> for more details...
Suppose you have a combinational circuit between two
registers driven by a clock. What will you do if the delay
of the combinational circuit is greater than your clock
signal? (You can't resize the combinational circuit
transistors)
- 6 Answers
- 14032 Views
- I also Faced
- E-Mail Answers
Answer Posted / ram
when there is a combo delay which is more than the clock
time period, though all the above can be a solution if the
delay is small, normally they mark it as a multi clock cycle
path.
| Is This Answer Correct ? | 3 Yes | 1 No |
Post New Answer View All Answers
What's the price in 1K quantity?
what is verilog?
Draw the stick diagram of a NOR gate. Optimize it
Implement a 2 I/P and gate using Tran gates?
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
If not into production, how far did you follow the design and why did not you see it into production?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
What was your role in the silicon evaluation or product ramp? What tools did you use?
Explain how Verilog is different to normal programming language?
What are the steps involved in designing an optimal pad ring?
Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
What does the above code synthesize to?
How to improve these parameters? (Cascode topology, use long channel transistors)
what is the difference between the TTL chips and CMOS chips?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
