Explain about stuck at fault models, scan design, BIST and IDDQ testing?

3 Answers   Intel,

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For CMOS logic, give the various techniques you know to minimize power consumption

0 Answers   Infosys,

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What are the limitations in increasing the power supply to reduce delay?

2 Answers   Infosys,

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What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

0 Answers   Infosys,

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What is latchup? Explain the methods used to prevent it?

2 Answers   Intel,

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What is clock feed through?

2 Answers   Intel,

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what is SCR (Silicon Controlled Rectifier)?

0 Answers  

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What is the difference between synchronous and asynchronous reset?

0 Answers  

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Mention what are the different gates where Boolean logic are applicable?

0 Answers  

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Explain what is Verilog?

0 Answers  

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Explain what is slack?

0 Answers  

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For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

0 Answers   Intel,

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