While using logic design, explain the various steps that r followed to obtain the desirable design in a well defined manner?
1 6075A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B = 1. Draw a state diagram for this Spec?
3 8581
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
Tell me how MOSFET works.
Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
What are the various regions of operation of mosfet? How are those regions used?
What is the difference between synchronous and asynchronous reset?
Explain what is slack?
Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
What is the function of tie-high and tie-low cells?
Describe the various effects of scaling?
What are the different design constraints occur in the synthesis phase?
Explain the three regions of operation of a mosfet.
why is the number of gate inputs to CMOS gates usually limited to four?
For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
