What are the main issues associated with multiprocessor caches and how might you solve them?

0 Answers   Intel,

---

Differences between Array and Booth Multipliers?

0 Answers   Intel,

---

What is Fowler-Nordheim Tunneling?

2 Answers   Intel,

---

Why is Extraction performed?

1 Answers   Intel,

---

What happens if we delay the enabling of Clock signal?

4 Answers  

---

---

Explain what is the depletion region?

0 Answers  

---

What are the changes that are provided to meet design power targets?

0 Answers  

---

Define threshold voltage?

32 Answers   College School Exams Tests, Intel, JHG, Wipro,

---

Explain the various MOSFET Capacitances & their significance?

1 Answers  

---

Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

---

What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

0 Answers   Infosys,

---

what is Channel length modulation?

2 Answers   Intel,

---