What happens to delay if you increase load capacitance?

3 Answers   Infosys,

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Differences between D-Latch and D flip-flop?

17 Answers   AIT, Intel, Sibridge Technologies,

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What are the different design constraints occur in the synthesis phase?

0 Answers  

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Differences between blocking and Non-blocking statements in Verilog?

5 Answers   Intel,

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For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

0 Answers   Intel,

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Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

0 Answers   Infosys,

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Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,

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A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B = 1. Draw a state diagram for this Spec?

3 Answers   Intel,

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What is the function of enhancement mode transistor?

0 Answers  

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Explain the Charge Sharing problem while sampling data from a Bus?

1 Answers  

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How binary number can give a signal or convert into a digital signal?

0 Answers  

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What is the difference between synchronous and asynchronous reset?

0 Answers  

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