In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

1 Answers   Intel,

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What is look up table in vlsi?

0 Answers  

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verify nmos passes good logic 0 and passes bad logic 1.also verify that pmos passes good logic 1 and passes bad logic 0.

2 Answers   Cosmic Circuits, HP,

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Explain the Various steps in Synthesis?

0 Answers   Intel,

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How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

0 Answers   Infosys,

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Why is OOPS called OOPS? (C++)

1 Answers   ARM, Intel,

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For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

0 Answers   Intel,

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Implement a function with both ratioes and domino logic and merits and demerits of each logic?

0 Answers   Intel,

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If not into production, how far did you follow the design and why did not you see it into production?

1 Answers   Intel,

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Explain what is slack?

0 Answers  

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Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

0 Answers   Infosys,

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Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?

3 Answers   Intel,

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