Describe the various effects of scaling?

0 Answers   Infosys,

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What is FPGA?

7 Answers   Intel,

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While using logic design, explain the various steps that r followed to obtain the desirable design in a well defined manner?

1 Answers   Intel,

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What is the difference between synchronous and asynchronous reset?

0 Answers  

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WHAT IS THE DIFFERENCE BETWEEN TESTING AND VERIFICATION OF VLSI CIRCUIT?

5 Answers   Intel, Wipro,

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Design an 8 is to 3 encoder using 4 is to encoder?

0 Answers   Intel,

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Implement a function with both ratioed and domino logic and merits and demerits of each logic?

0 Answers   Intel,

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Give the cross-sectional diagram of the cmos.

0 Answers  

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what is charge sharing?

0 Answers   Intel,

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For f = AB+CD if B is S-a-1, what r the test vectors needed to detect the fault?

5 Answers   Intel,

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What are the steps required to solve setup and hold violations in vlsi?

0 Answers  

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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