What?s the critical path in a SRAM?

2 Answers   Infosys, Intel, Texas,

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what is Early effects and their physical origin.

1 Answers  

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What types of high speed CMOS circuits have you designed?

0 Answers   Intel,

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In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

0 Answers   Infosys,

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What are set up time & hold time constraints? What do they signify?

3 Answers  

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What is a D-latch? Write the VHDL Code for it?

3 Answers   Intel,

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Explain Cross section of an NMOS transistor?

0 Answers   Intel,

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How can you model a SRAM at RTL Level?

1 Answers  

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How can you model a SRAM at RTL Level?

0 Answers   Infosys,

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Explain how Verilog is different to normal programming language?

0 Answers  

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What are the various regions of operation of mosfet? How are those regions used?

0 Answers  

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What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

0 Answers   Infosys,

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