Explain why is the number of gate inputs to cmos gates usually limited to four?


No Answer is Posted For this Question
Be the First to Post Answer

Post New Answer

More VLSI Interview Questions

For f = AB+CD if B is S-a-1, what r the test vectors needed to detect the fault?

5 Answers   Intel,


what is the difference between the TTL chips and CMOS chips?

0 Answers  


what is a sequential circuit?

0 Answers  


Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

0 Answers   Infosys,


Why does the present vlsi circuits use mosfets instead of bjts?

0 Answers  






What is clock feed through?

2 Answers   Intel,


How can you construct both PMOS and NMOS on a single substrate?

0 Answers   IBM, Intel,


What is interrupt latency?

3 Answers  


Explain Basic Stuff related to Perl?

0 Answers   Intel,


If not into production, how far did you follow the design and why did not you see it into production?

0 Answers   Intel,


Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)

6 Answers  


What are the different design techniques required to create a layout for digital circuits?

0 Answers  


Categories