For f = AB+CD if B is S-a-1, what r the test vectors needed
to detect the fault?
Answers were Sorted based on User's Feedback
Answer / deepak
Give the test vector A = 1, B = 0, C = 0 and D = 0.
If B is not stuck at 1, the output would be zero else 1.
So test vector 1000 can detect the stuck at 1 fault of B.
| Is This Answer Correct ? | 26 Yes | 2 No |
Answer / ranadheer reddy s
you can go for path sensitization method the test vectors
for this s-a-1 fault are
1000
1010
1001
that's it simple....
| Is This Answer Correct ? | 6 Yes | 0 No |
Answer / yashwanth.jada
1)Analysis: S-a-1 in B
2)Simulate the fault location (B): Give 0 (compliment of S-a-F) as input at B, this way one can distinguish True value/Faulty value.
3)Propagate the faulty value to primary output (f): A has to be a non controlling value i.e 1 in order to propagate the fault (0/1 at B) to AB AND gate. In order to see the fault effect at output f, the other input of OR gate has to be a non-controlling value i.e 0.
4)Justification for 0 at OR gate input: Atleast one of the inputs between C and D has to be 0.
5)Final test vector for B S-a-1: 100X or 10X0 {(1000),(1001),(1010)}
| Is This Answer Correct ? | 1 Yes | 0 No |
Answer / ajit
Walking Ones will find out the Struck-at-1.
0001
0010
0100
1000 : At this point Error will be detected
Or Walking Zero can also find out.
1110
1101
1011 : At this point Error will be detectged
0111
| Is This Answer Correct ? | 1 Yes | 9 No |
What are the different gates where boolean logic are applicable?
What are the total number of lines written by you in C/C++? What compiler was used?
Explain what is multiplexer?
If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
what is a sequential circuit?
Need to convert this VHDL code into VLSI verilog code? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of specific package--- ENTITY tollbooth2 IS PORT (Clock,car_s,RE : IN STD_LOGIC; coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); r_light,g_light,alarm : OUT STD_LOGIC); END tollbooth2; ARCHITECTURE Behav OF tollbooth2 IS TYPE state_type IS (NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE D); ------GOTZERO = PAID $0.00--------- ------GOTFIV = PAID $0.05---------- ------GOTTEN = PAID $0.10---------- ------GOTFIF = PAID $0.15---------- ------GOTTWEN = PAID $0.20--------- SIGNAL present_state,next_state : state_type; BEGIN -----Next state is identified using present state,car & coin sensors------ PROCESS(present_state,car_s,coin_s) BEGIN CASE present_state IS WHEN NO_CAR => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= NO_CAR; END IF; WHEN GOTZERO => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTZERO; ELSIF (coin_s = "01") THEN next_state <= GOTFIV; ELSIF (coin_s ="10") THEN next_state <= GOTTEN; END IF; WHEN GOTFIV=> IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIV; ELSIF (coin_s = "01") THEN next_state <= GOTTEN; ELSIF (coin_s <= "10") THEN next_state <= GOTFIV; END IF; WHEN GOTTEN => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s ="00") THEN next_state <= GOTTEN; ELSIF (coin_s="01") THEN next_state <= GOTFIV; ELSIF (coin_s="10") THEN next_state <= GOTTWEN; END IF; WHEN GOTFIF => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIF; ELSIF (coin_s ="01") THEN next_state <= GOTTWEN; ELSIF (coin_s = "10") THEN next_state <= GOTTWEN; END IF; WHEN GOTTWEN => next_state <= CAR_PAID; WHEN CAR_PAID => IF (car_s = '0') THEN next_state <= NO_CAR; ELSE next_state<= CAR_PAID; END IF; WHEN CHEATED => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= CHEATED; END IF; END CASE; END PROCESS;-----End of Process 1 -------PROCESS 2 for STATE REGISTER CLOCKING-------- PROCESS(Clock,RE) BEGIN IF RE = '1' THEN present_state <= GOTZERO; ----When the clock changes from low to high,the state of the system ----stored in next_state becomes the present state----- ELSIF Clock'EVENT AND Clock ='1' THEN present_state <= next_state; END IF; END PROCESS;-----End of Process 2------- --------------------------------------------------------- -----Conditional signal assignment statements---------- r_light <= '0' WHEN present_state = CAR_PAID ELSE '1'; g_light <= '1' WHEN present_state = CAR_PAID ELSE '0'; alarm <= '1' WHEN present_state = CHEATED ELSE '0'; END Behav;
How does a Bandgap Voltage reference work?
What are the different ways in which antenna violation can be prevented?
Explain the usage of the shared SPI bus?
What are the two types of noise of MOSFET, how to eliminate them?(Thermal and Flicker).
Explain CMOS Inverter transfer characteristics?
Are you familiar with VHDL and/or Verilog?