For f = AB+CD if B is S-a-1, what r the test vectors needed
to detect the fault?
- 5 Answers
- 12189 Views
- Intel, I also Faced
- E-Mail Answers
Answers were Sorted based on User's Feedback
Answer / deepak
Give the test vector A = 1, B = 0, C = 0 and D = 0.
If B is not stuck at 1, the output would be zero else 1.
So test vector 1000 can detect the stuck at 1 fault of B.
| Is This Answer Correct ? | 26 Yes | 2 No |
Answer / ranadheer reddy s
you can go for path sensitization method the test vectors
for this s-a-1 fault are
1000
1010
1001
that's it simple....
| Is This Answer Correct ? | 5 Yes | 0 No |
Answer / yashwanth.jada
1)Analysis: S-a-1 in B
2)Simulate the fault location (B): Give 0 (compliment of S-a-F) as input at B, this way one can distinguish True value/Faulty value.
3)Propagate the faulty value to primary output (f): A has to be a non controlling value i.e 1 in order to propagate the fault (0/1 at B) to AB AND gate. In order to see the fault effect at output f, the other input of OR gate has to be a non-controlling value i.e 0.
4)Justification for 0 at OR gate input: Atleast one of the inputs between C and D has to be 0.
5)Final test vector for B S-a-1: 100X or 10X0 {(1000),(1001),(1010)}
| Is This Answer Correct ? | 1 Yes | 0 No |
Answer / ajit
Walking Ones will find out the Struck-at-1.
0001
0010
0100
1000 : At this point Error will be detected
Or Walking Zero can also find out.
1110
1101
1011 : At this point Error will be detectged
0111
| Is This Answer Correct ? | 1 Yes | 9 No |
What is the critical path in a SRAM?
What is charge sharing?
2 Answers Cypress Semiconductor, Intel,
What are the different design techniques required to create a layout for digital circuits?
What is the difference between cmos and bipolar technologies?
Explain the various MOSFET Capacitances & their significance?
Are you familiar with VHDL and/or Verilog?
Who provides the DRC rules?
What products have you designed which have entered high volume production?
Are you familiar with VHDL and/or Verilog?
Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
For a 0.18um and 0.8um technology MOSFET, which has a higher cutoff frequency?
86 Family 
