Interested to Buy Any Domain ? << Click Here >> for more details...
For f = AB+CD if B is S-a-1, what r the test vectors needed
to detect the fault?
- 5 Answers
- 13840 Views
- Intel, I also Faced
- E-Mail Answers
Answer Posted / yashwanth.jada
1)Analysis: S-a-1 in B
2)Simulate the fault location (B): Give 0 (compliment of S-a-F) as input at B, this way one can distinguish True value/Faulty value.
3)Propagate the faulty value to primary output (f): A has to be a non controlling value i.e 1 in order to propagate the fault (0/1 at B) to AB AND gate. In order to see the fault effect at output f, the other input of OR gate has to be a non-controlling value i.e 0.
4)Justification for 0 at OR gate input: Atleast one of the inputs between C and D has to be 0.
5)Final test vector for B S-a-1: 100X or 10X0 {(1000),(1001),(1010)}
| Is This Answer Correct ? | 1 Yes | 0 No |
Post New Answer View All Answers
Explain how binary number can give a signal or convert into a digital signal?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
Write a program to explain the comparator?
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
Why does the present vlsi circuits use mosfets instead of bjts?
Differences between Array and Booth Multipliers?
If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?
What are the steps involved in preventing the metastability?
What transistor level design tools are you proficient with? What types of designs were they used on?
Differences between IRSIM and SPICE?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
What are the different gates where boolean logic are applicable?
What is the main function of metastability in vsdl?
