Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...

What is charge sharing?

Answer Posted / gk

it is like suppose you have two capacitors connected in series/parallel there will be charge sharing. in mosfet we want the gate capacitance to control channel only.but gate to drain overlapping(coupling) at the end of channel creates capacitance(Cgd) similarly at source also. there is PN junction depletion capacitance at drain/source with substrate completes path. This path creates coupling of input to drain.

Is This Answer Correct ?    3 Yes 0 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

1133


What are the different measures that are required to achieve the design for better yield?

1218


Explain how MOSFET works?

3234


What are the different gates where boolean logic are applicable?

1068


Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

1080


Write a VLSI program that implements a toll booth controller?

3986


What are the different design constraints occur in the synthesis phase?

1101


You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

1573


what is a sequential circuit?

1170


What is the difference between the mealy and moore state machine?

1119


Draw a 6-T SRAM Cell and explain the Read and Write operations

1289


How binary number can give a signal or convert into a digital signal?

1244


Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3867


what are three regions of operation of MOSFET and how are they used?

1242


What is Noise Margin? Explain the procedure to determine Noise Margin?

2457