For CMOS logic, give the various techniques you know to minimize power consumption
- 0 Answers
- 851 Views
- Infosys, I also Faced
- E-Mail Answers
No Answer is Posted For this Question
Be the First to Post Answer
What are the steps involved in designing an optimal pad ring?
Are you familiar with the term snooping?
What are the various regions of operation of mosfet? How are those regions used?
Draw the Layout of an Inverter?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
What happens if we delay the enabling of Clock signal?
Give the various techniques you know to minimize power consumption?
What is the most complicated/valuable program you written in C/C++?
23 Answers HCL, IBM, Intel, TCS, TVS, Wipro,
For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
How to improve these parameters? (Cascode topology, use long channel transistors)
what is the use of defpararm?
86 Family 
