For CMOS logic, give the various techniques you know to minimize power consumption
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Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)
Explain Clock Skew?
Working of a 2-stage OPAMP?
Explain how MOSFET works?
Have you studied buses? What types?
What is charge sharing?
2 Answers Cypress Semiconductor, Intel,
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
Explain what is slack?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?
If the substrate doping concentration increase, or temperature increases, how will Vt change? it increase or decrease?
If not into production, how far did you follow the design and why did not you see it into production?