Draw the SRAM Write Circuitry

0 Answers   Infosys,

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Implement F= not (AB+CD) using CMOS gates?

1 Answers   Intel,

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Mention what are three regions of operation of mosfet and how are they used?

0 Answers  

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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What are the different measures that are required to achieve the design for better yield?

0 Answers  

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Are you familiar with VHDL and/or Verilog?

1 Answers   Intel,

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Are you familiar with the term MESI?

1 Answers   Intel,

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For f = AB+CD if B is S-a-1, what r the test vectors needed to detect the fault?

5 Answers   Intel,

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What is Fermi level?

5 Answers  

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Explain what is scr (silicon controlled rectifier)?

0 Answers  

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Who provides the DRC rules?

5 Answers   Intel,

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Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?

13 Answers   Intel,

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