Answer / salla nagaraju

When sampling data from a bus using CMOS transmission gates or multiplexers, charge sharing can occur, leading to incorrect logic levels at the output.

what is a sequential circuit?

1 Answers  

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What was your role in the silicon evaluation or product ramp? What tools did you use?

1 Answers   Intel,

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How many bit combinations are there in a byte?

6 Answers   Intel,

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Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?

3 Answers   Intel,

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Explain CMOS Inverter transfer characteristics?

1 Answers   ADS,

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Are you familiar with VHDL and/or Verilog?

1 Answers   Intel,

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Are you familiar with the term MESI?

1 Answers   Intel,

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Explain Clock Skew?

6 Answers   Intel, nvidia,

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What is component binding?

2 Answers   Intel,

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What are the Factors affecting Power Consumption on a chip?

1 Answers   Intel,

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verify nmos passes good logic 0 and passes bad logic 1.also verify that pmos passes good logic 1 and passes bad logic 0.

2 Answers   Cosmic Circuits, HP,

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For CMOS logic, give the various techniques you know to minimize power consumption

1 Answers   Infosys,

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