Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,

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Explain why is the number of gate inputs to cmos gates usually limited to four?

0 Answers  

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Implement a function with both ratioes and domino logic and merits and demerits of each logic?

0 Answers   Intel,

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What happens to delay if we include a resistance at the output of a CMOS circuit?

1 Answers   Infosys,

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What is the difference between synchronous and asynchronous reset?

0 Answers  

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Draw the Layout of an Inverter?

0 Answers   Intel,

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Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?

1 Answers   IIT, Intel,

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You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

4 Answers   Intel,

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what is Latch up?How to avoid Latch up?

3 Answers  

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What types of high speed CMOS circuits have you designed?

0 Answers   Intel,

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What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

0 Answers   Intel,

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A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B = 1. Draw a state diagram for this Spec?

3 Answers   Intel,

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