For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

0 Answers   Intel,

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In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

3 Answers   IBM, Intel, nvidia,

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Insights of a Tri-State Inverter?

3 Answers   Intel,

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Explain the Charge Sharing problem while sampling data from a Bus?

1 Answers  

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What is pipelining and how can we increase throughput using pipelining?

1 Answers   Intel,

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Explain the working of differential sense amplifier?

1 Answers  

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Insights of a 2 input NAND gate. Explain the working?

1 Answers   Intel,

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For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

3 Answers   Intel,

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How does a pn junction works?

2 Answers   Wipro,

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How do you detect a sequence of "1101" arriving serially from a signal line?

7 Answers   nvidia,

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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What are the ways to Optimize the Performance of a Difference Amplifier?

0 Answers  

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