While using logic design, explain the various steps that r followed to obtain the desirable design in a well defined manner?

1 Answers   Intel,

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For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

0 Answers   Infosys,

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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What is setup time and hold time?

1 Answers   Intel,

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Tell me how MOSFET works.

0 Answers  

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Explain ASIC Design Flow?

2 Answers   Intel, JK Associates, Mind Tree,

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what is Early effects and their physical origin.

1 Answers  

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What?s the critical path in a SRAM?

2 Answers   Infosys, Intel, Texas,

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How does Resistance of the metal lines vary with increasing thickness and increasing length?

3 Answers   Infosys,

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What is SPICE?

4 Answers   Intel,

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Explain why is the number of gate inputs to cmos gates usually limited to four?

0 Answers  

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Explain how binary number can give a signal or convert into a digital signal?

0 Answers  

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