How many bit combinations are there in a byte?
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What are set up time & hold time constraints? What do they signify?
Have you studied buses? What types?
what is verilog?
What does the above code synthesize to?
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
Are you familiar with the term MESI?
How does Resistance of the metal lines vary with increasing thickness and increasing length?
What are the main issues associated with multiprocessor caches and how might you solve them?
what is Channel length modulation?
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
What transistor level design tools are you proficient with? What types of designs were they used on?