What happens to delay if you increase load capacitance?
Answers were Sorted based on User's Feedback
Answer / jaya suriya
pd=f *c* vdd^2
power dissipation get increases.....
propagation delay get increases....
so speed of the circuit get decreased...
| Is This Answer Correct ? | 19 Yes | 0 No |
Answer / arpan
If load capacitance is increased then time require to charge
the capacitance increases, so the rise time increases which
in turn increases the delay.
| Is This Answer Correct ? | 7 Yes | 1 No |
Explain depletion region.
What transistor level design tools are you proficient with? What types of designs were they used on?
How can you construct both PMOS and NMOS on a single substrate?
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
What is the difference between the mealy and moore state machine?
Write a program to explain the comparator?
Have you studied buses? What types?
Draw the Layout of an Inverter?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
What products have you designed which have entered high volume production?
Explain sizing of the inverter?
Tell me how BJT works.