What is Noise Margin? Explain the procedure to determine
Noise Margin?
Answers were Sorted based on User's Feedback
Answer / pradeep
Noise margin simply means margin for noise. it can tolerate
some amount of noise. The senders must be held at higher
standards than the receivers. For a 5V level, a voltage
above 4.5V is considered 1, and for receiver the voltage
above 3.5V is considered 1. therefore, the noise margin
4.5-3.5=1V.
it is deigned by looking at voltage transfer function.
| Is This Answer Correct ? | 49 Yes | 3 No |
Answer / bhau
In digital logic design the general representation of input
and output are High and low level (1's and 0's). In actual
case when the input signal transitions the output switches
to full swing before the input has reached its full swing.
The minimum signal level to get a out put High or low is
called VIH, VIL (For inversion stage Input for getting full
output low swing and input for getting full output high
swing). For the interoperability of this logic device i.e.
to use tihs output directly to feed into next stage without
level shifting the VIL > VOL, similarly VIH < VOH. In such
condition when logic swing VIL is enough to get full swing
on Output the noise margin will be VOL-VIL. Similarly NM
for signal transitioning high is VOH-VIH.
| Is This Answer Correct ? | 52 Yes | 27 No |
Answer / shubham sharma
"noise margine is the max. voltage that can be added to the
logic gate input which will not affect the output."
voh>vih>vil>vol
vil=0,vol=0.
vih=1,voh=1.
| Is This Answer Correct ? | 11 Yes | 4 No |
Answer / bhau
In digital logic design the general representation of input
and output are High and low level (1's and 0's). In actual
case when the input signal transitions the output switches
to full swing before the input has reached its full swing.
The minimum signal level to get a out put High or low is
called VIH, VIL (For inversion stage Input for getting full
output low swing and input for getting full output high
swing). For the interoperability of this logic device i.e.
to use tihs output directly to feed into next stage without
level shifting the VIL > VOL, similarly VIH < VOH. In such
condition when logic swing VIL is enough to get full swing
on Output the noise margin will be VOL-VIL. Similarly NM
for signal transitioning high is VOH-VIH.
| Is This Answer Correct ? | 12 Yes | 36 No |
Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?
Explain the various Capacitances associated with a transistor and which one of them is the most prominent?
what is Early effects and their physical origin.
What are the different gates where boolean logic are applicable?
How to find the read failiure probablity in SRAM?
What is the difference between cmos and bipolar technologies?
Given a circuit and asked to tell the output voltages of that circuit?
1 Answers Intel, Omega Healthcare,
Explain the working of differential sense amplifier?
Give the various techniques you know to minimize power consumption?
Explain the difference between write through and write back cache.
what is the difference between the TTL chips and CMOS chips?
If the substrate doping concentration increase, or temperature increases, how will Vt change? it increase or decrease?