What is Noise Margin? Explain the procedure to determine
Noise Margin?
Answers were Sorted based on User's Feedback
Answer / pradeep
Noise margin simply means margin for noise. it can tolerate
some amount of noise. The senders must be held at higher
standards than the receivers. For a 5V level, a voltage
above 4.5V is considered 1, and for receiver the voltage
above 3.5V is considered 1. therefore, the noise margin
4.5-3.5=1V.
it is deigned by looking at voltage transfer function.
| Is This Answer Correct ? | 49 Yes | 3 No |
Answer / bhau
In digital logic design the general representation of input
and output are High and low level (1's and 0's). In actual
case when the input signal transitions the output switches
to full swing before the input has reached its full swing.
The minimum signal level to get a out put High or low is
called VIH, VIL (For inversion stage Input for getting full
output low swing and input for getting full output high
swing). For the interoperability of this logic device i.e.
to use tihs output directly to feed into next stage without
level shifting the VIL > VOL, similarly VIH < VOH. In such
condition when logic swing VIL is enough to get full swing
on Output the noise margin will be VOL-VIL. Similarly NM
for signal transitioning high is VOH-VIH.
| Is This Answer Correct ? | 52 Yes | 27 No |
Answer / shubham sharma
"noise margine is the max. voltage that can be added to the
logic gate input which will not affect the output."
voh>vih>vil>vol
vil=0,vol=0.
vih=1,voh=1.
| Is This Answer Correct ? | 11 Yes | 4 No |
Answer / bhau
In digital logic design the general representation of input
and output are High and low level (1's and 0's). In actual
case when the input signal transitions the output switches
to full swing before the input has reached its full swing.
The minimum signal level to get a out put High or low is
called VIH, VIL (For inversion stage Input for getting full
output low swing and input for getting full output high
swing). For the interoperability of this logic device i.e.
to use tihs output directly to feed into next stage without
level shifting the VIL > VOL, similarly VIH < VOH. In such
condition when logic swing VIL is enough to get full swing
on Output the noise margin will be VOL-VIL. Similarly NM
for signal transitioning high is VOH-VIH.
| Is This Answer Correct ? | 12 Yes | 36 No |
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.
6-T XOR gate?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
What was your role in the silicon evaluation or product ramp? What tools did you use?
what is a sequential circuit?
What is Cross Talk?
If not into production, how far did you follow the design and why did not you see it into production?
Tell me how MOSFET works.
Draw the stick diagram of a NOR gate. Optimize it
WHAT IS THE DIFFERENCE BETWEEN TESTING AND VERIFICATION OF VLSI CIRCUIT?
How does Resistance of the metal lines vary with increasing thickness and increasing length?