Answer Posted / bhau

In digital logic design the general representation of input
and output are High and low level (1's and 0's). In actual
case when the input signal transitions the output switches
to full swing before the input has reached its full swing.
The minimum signal level to get a out put High or low is
called VIH, VIL (For inversion stage Input for getting full
output low swing and input for getting full output high
swing). For the interoperability of this logic device i.e.
to use tihs output directly to feed into next stage without
level shifting the VIL > VOL, similarly VIH < VOH. In such
condition when logic swing VIL is enough to get full swing
on Output the noise margin will be VOL-VIL. Similarly NM
for signal transitioning high is VOH-VIH.

Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

1149

---

What are the different design constraints occur in the synthesis phase?

1101

---

How does Vbe and Ic change with temperature?

3516

---

what is verilog?

1139

---

What are the main issues associated with multiprocessor caches and how might you solve them?

2227

---

what is the use of defpararm?

1145

---

How about voltage source?

2267

---

What is the critical path in a SRAM?

3196

---

How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

1206

---

Draw the Layout of an Inverter?

2505

---

Mention what are three regions of operation of mosfet and how are they used?

1082

---

What was your role in the silicon evaluation or product ramp? What tools did you use?

2318

---

Explain about 6-T XOR gate?

1274

---

What happens if we use an Inverter instead of the Differential Sense Amplifier?

3314

---

What is look up table in vlsi?

986

---