Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,

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Explain about stuck at fault models, scan design, BIST and IDDQ testing?

3 Answers   Intel,

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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What is Cross Talk?

4 Answers   Intel,

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What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

0 Answers   Intel,

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What happens if we increase the number of contacts or via from one metal layer to the next?

1 Answers   Infosys,

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Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

0 Answers   Infosys,

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.

0 Answers   Infosys,

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Give the expression for calculating Delay in CMOS circuit?

1 Answers   Infosys,

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What happens if we use an Inverter instead of the Differential Sense Amplifier?

0 Answers  

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What transistor level design tools are you proficient with? What types of designs were they used on?

0 Answers   Intel,

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What are the different design techniques required to create a layout for digital circuits?

0 Answers  

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