In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

1195

How does a Bandgap Voltage reference work?

3909

Explain the three regions of operation of a mosfet.

1098

Explain the working of 4-bit Up/down Counter?

4439

In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

1219

How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

1207

Describe the various effects of scaling?

4795

What are the changes that are provided to meet design power targets?

1122

What does it mean “the channel is pinched off”?

1358

what is SCR (Silicon Controlled Rectifier)?

1047

What are the different design techniques required to create a layout for digital circuits?

1043

What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

1338

Explain the Working of a 2-stage OPAMP?

1198

What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

3267

Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

1149