Id vs. Vds Characteristics of NMOS and PMOS transistors?
For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
Insights of an inverter. Explain the working?
Explain what is slack?
Explain Cross section of an NMOS transistor?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B = 1. Draw a state diagram for this Spec?
Insights of a 4bit adder/Sub Circuit?
Explain the operation considering a two processor computer system with a cache for each processor.
Explain why & how a MOSFET works?
Explain how Verilog is different to normal programming language?
Mention what are three regions of operation of mosfet and how are they used?
What are the various regions of operation of mosfet? How are those regions used?