Why do we need both PMOS and NMOS transistors to implement a
pass gate?
Answers were Sorted based on User's Feedback
Answer / eyeman
Any logic gate can be constructed using pMOS and nMOS
transistor. nMOS being negatively doped silicon, rich in
electrons while pMOS is positively doped silicon, rich in
holes. Thus pMOS transistors are great at transmitting a
logic 1 voltage without signal loss, but the same cannot be
said about logic 0 voltages. Having 0 V at one side of a
conducting pMOS transistor yields a voltage at the other
side somewhat higher than 0 V. nMOS transistors are good to
pass logic 0 but not so good at passing logic 1. Thus the
best possible transmission behavior can be obtained by
combining both kinds of transistors. This is the trick in
pass gate.
| Is This Answer Correct ? | 16 Yes | 2 No |
Answer / pushpa
both are not perfect at 0 or 1,pmos is perfect of 1 but not 0,so nmos is perfect of 0 not 1..so we are use the both
| Is This Answer Correct ? | 1 Yes | 0 No |
Answer / akshay aggarwal
nmos output is inverted.for eg.-
if we have to make y=a+b
we will design it using nmos....but we get the output
ybar = a + b
to get y instead of ybar we use a complementary pmos circuit
| Is This Answer Correct ? | 1 Yes | 6 No |
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
What is the function of chain reordering?
Explain the working of differential sense amplifier?
If not into production, how far did you follow the design and why did not you see it into production?
Explain the Working of a 2-stage OPAMP?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
For CMOS logic, give the various techniques you know to minimize power consumption
what is the difference between the testing and verification?
In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
What are the various regions of operation of mosfet? How are those regions used?