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What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
3206What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
1 4925Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
3074What transistor level design tools are you proficient with? What types of designs were they used on?
5022If not into production, how far did you follow the design and why did not you see it into production?
1 5183
What's the price in 1K quantity?
Explain how MOSFET works?
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
Basic Stuff related to Perl?
what is Slack?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
why is the number of gate inputs to CMOS gates usually limited to four?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.
What happens if we use an Inverter instead of the Differential Sense Amplifier?
what is multiplexer?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
Explain why present VLSI circuits use MOSFETs instead of BJTs?
For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?
Explain Cross section of a PMOS transistor?
