Answer / guest

jigs and fixtures

Explain Clock Skew?

6 Answers   Intel, nvidia,

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What are the Factors affecting Power Consumption on a chip?

0 Answers   Intel,

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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What are the changes that are provided to meet design power targets?

0 Answers  

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In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

3 Answers   IBM, Intel, nvidia,

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What is the function of tie-high and tie-low cells?

0 Answers  

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What is Fowler-Nordheim Tunneling?

2 Answers   Intel,

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What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

0 Answers   Infosys,

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Explain Basic Stuff related to Perl?

0 Answers   Intel,

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Implement F= not (AB+CD) using CMOS gates?

0 Answers   Intel,

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what is body effect?

1 Answers  

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What is Fermi level?

5 Answers  

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