Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
4 12490For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
3 10141Explain the operation considering a two processor computer system with a cache for each processor.
2341Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
1 16643In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
3 18830You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
4 14331
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
why is the number of gate inputs to CMOS gates usually limited to four?
Implement F= not (AB+CD) using CMOS gates?
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
What are the Advantages and disadvantages of Mealy and Moore?
Explain the Charge Sharing problem while sampling data from a Bus?
What are the different classification of the timing control?
For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
What is look up table in vlsi?
Explain what is multiplexer?
What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
What types of high speed CMOS circuits have you designed?
Explain depletion region.
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
