Answer / narendra

issue : Cache coherency or Data coherency. The problem is
all the processors cache should have exactly the same
shared data (cohenrent data). and there are races possible
with multiprocessors.

possible solution: use one central cache controller which
will get all the read/write requests from all the
processors and peripherals so that it can make sure there
are no races and cache coherency is maintained.

Are you familiar with the term MESI?

0 Answers   Intel,

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Explain what is the depletion region?

0 Answers  

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verify nmos passes good logic 0 and passes bad logic 1.also verify that pmos passes good logic 1 and passes bad logic 0.

2 Answers   Cosmic Circuits, HP,

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Are you familiar with VHDL and/or Verilog?

17 Answers   Intel,

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Why is Extraction performed?

1 Answers   Intel,

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Explain the working of differential sense amplifier?

1 Answers  

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Explain Cross section of a PMOS transistor?

0 Answers   Intel,

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What is the difference between synchronous and asynchronous reset?

0 Answers  

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If not into production, how far did you follow the design and why did not you see it into production?

1 Answers   Intel,

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Explain various adders and diff between them?

1 Answers   Intel,

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what are three regions of operation of MOSFET and how are they used?

0 Answers  

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Give the various techniques you know to minimize power consumption?

5 Answers  

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