Answer / narendra

issue : Cache coherency or Data coherency. The problem is
all the processors cache should have exactly the same
shared data (cohenrent data). and there are races possible
with multiprocessors.

possible solution: use one central cache controller which
will get all the read/write requests from all the
processors and peripherals so that it can make sure there
are no races and cache coherency is maintained.

Have you studied buses? What types?

1 Answers   Intel,

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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WHAT IS THE DIFFERENCE BETWEEN TESTING AND VERIFICATION OF VLSI CIRCUIT?

5 Answers   Intel, Wipro,

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What is Noise Margin? Explain the procedure to determine Noise Margin?

4 Answers   Amkor, Cisco, Infosys, Intel,

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Explain the difference between write through and write back cache.

2 Answers   Intel,

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What is Cross Talk?

4 Answers   Intel,

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What are the different ways in which antenna violation can be prevented?

0 Answers  

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Factors affecting Power Consumption on a chip?

7 Answers   Intel,

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Describe the various effects of scaling?

0 Answers   Infosys,

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In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

0 Answers   Infosys,

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What types of high speed CMOS circuits have you designed?

0 Answers   Intel,

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Explain what is the use of defpararm?

0 Answers  

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