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Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
1668You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
1576What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
1349How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
1212For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
1282Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
1487Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
1302For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
1464Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
1308Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
1465
What is threshold voltage?
Are you familiar with the term MESI?
What are the Advantages and disadvantages of Mealy and Moore?
What happens if we delay the enabling of Clock signal?
Differences between IRSIM and SPICE?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
What is look up table in vlsi?
what are three regions of operation of MOSFET and how are they used?
What transistor level design tools are you proficient with? What types of designs were they used on?
How binary number can give a signal or convert into a digital signal?
what is the difference between the TTL chips and CMOS chips?
How can you model a SRAM at RTL Level?
If not into production, how far did you follow the design and why did not you see it into production?
Insights of a 4bit adder/Sub Circuit?
Explain the Working of a 2-stage OPAMP?
