Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
1067You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
955What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
766For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
710Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
847Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
814For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
942Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
783Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
864
What are the different ways in which antenna violation can be prevented?
What is Noise Margin? Explain the procedure to determine Noise Margin?
What does the above code synthesize to?
What is the difference between cmos and bipolar technologies?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
How binary number can give a signal or convert into a digital signal?
Mention what are three regions of operation of mosfet and how are they used?
How about voltage source?
Explain what is the depletion region?
If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
What is the difference between nmos and pmos technologies?
Implement a function with both ratioes and domino logic and merits and demerits of each logic?
What is the critical path in a SRAM?
what is multiplexer?
