Embedded Systems Interview Questions
Questions Answers Views Company eMail

Difference between 80286 and 80287

Mascot,

2 6489

In a processor these are 120 instructions . Bits needed to impliment this instructions [a] 6 [b] 7 [c] 10 [d] none

Wipro,

2 7023

In 8085 microprocessor READY signal does.which of the following is incorrect statements [a]It is input to the microprocessor [b] It sequences the instructions

Wipro,

2 6397




Return address will be returned by function to

Wipro,

2 3390

load a mul a store t1 load b mul b store t2 mul t2 add t1 then the content in accumulator is

Wipro,

2 4588

In 8085 microprocessor READY signal does.which of the following is incorrect statements [a]It is input to the microprocessor [b] It sequences the instructions

Wipro,

4 6467

what is conductance and valence band?

1 2947

What is Fermi level?

5 4401

How does Vbe and Ic change with temperature?

Qualcomm,

1676

If the substrate doping concentration increase, or temperature increases, how will Vt change? it increase or decrease?

1092

what is Channel length modulation?

Intel,

1381

what is the doping?

5 2920

How does a pn junction works?

Wipro,

1 3438

What is the depletion region?

1 2779

Tell me the parameters as many as possible you know that used to character an amplifier?

807







Un-Answered Questions { Embedded Systems }

How do you size NMOS and PMOS transistors to increase the threshold voltage?

1340


Explain the operation considering a two processor computer system with a cache for each processor.

1260


What types of CMOS memories have you designed? What were their size? Speed?

1344


Working of a 2-stage OPAMP?

1494


How to improve these parameters? (Cascode topology, use long channel transistors)

760


what is the command/instruction in ARM that does not do anything or does not execute any instruction ? (except NOP instruction)

1798


What does the above code synthesize to?

909


Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

47


Program to print the 32 number in form of binary, Hexa and ASCI.

1601


Cross section of a PMOS transistor?

2871


What transistor level design tools are you proficient with? What types of designs were they used on?

837


Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

2292


If not into production, how far did you follow the design and why did not you see it into production?

739


What is the ideal input and output resistance of a current source?

1557


Need to convert this VHDL code into VLSI verilog code? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of specific package--- ENTITY tollbooth2 IS PORT (Clock,car_s,RE : IN STD_LOGIC; coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); r_light,g_light,alarm : OUT STD_LOGIC); END tollbooth2; ARCHITECTURE Behav OF tollbooth2 IS TYPE state_type IS (NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE D); ------GOTZERO = PAID $0.00--------- ------GOTFIV = PAID $0.05---------- ------GOTTEN = PAID $0.10---------- ------GOTFIF = PAID $0.15---------- ------GOTTWEN = PAID $0.20--------- SIGNAL present_state,next_state : state_type; BEGIN -----Next state is identified using present state,car & coin sensors------ PROCESS(present_state,car_s,coin_s) BEGIN CASE present_state IS WHEN NO_CAR => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= NO_CAR; END IF; WHEN GOTZERO => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTZERO; ELSIF (coin_s = "01") THEN next_state <= GOTFIV; ELSIF (coin_s ="10") THEN next_state <= GOTTEN; END IF; WHEN GOTFIV=> IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIV; ELSIF (coin_s = "01") THEN next_state <= GOTTEN; ELSIF (coin_s <= "10") THEN next_state <= GOTFIV; END IF; WHEN GOTTEN => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s ="00") THEN next_state <= GOTTEN; ELSIF (coin_s="01") THEN next_state <= GOTFIV; ELSIF (coin_s="10") THEN next_state <= GOTTWEN; END IF; WHEN GOTFIF => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIF; ELSIF (coin_s ="01") THEN next_state <= GOTTWEN; ELSIF (coin_s = "10") THEN next_state <= GOTTWEN; END IF; WHEN GOTTWEN => next_state <= CAR_PAID; WHEN CAR_PAID => IF (car_s = '0') THEN next_state <= NO_CAR; ELSE next_state<= CAR_PAID; END IF; WHEN CHEATED => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= CHEATED; END IF; END CASE; END PROCESS;-----End of Process 1 -------PROCESS 2 for STATE REGISTER CLOCKING-------- PROCESS(Clock,RE) BEGIN IF RE = '1' THEN present_state <= GOTZERO; ----When the clock changes from low to high,the state of the system ----stored in next_state becomes the present state----- ELSIF Clock'EVENT AND Clock ='1' THEN present_state <= next_state; END IF; END PROCESS;-----End of Process 2------- --------------------------------------------------------- -----Conditional signal assignment statements---------- r_light <= '0' WHEN present_state = CAR_PAID ELSE '1'; g_light <= '1' WHEN present_state = CAR_PAID ELSE '0'; alarm <= '1' WHEN present_state = CHEATED ELSE '0'; END Behav;

3596