VLSI Interview Questions, Answers for Freshers and Experienced asked in various Company Job Interviews

VLSI Interview Questions

Questions Answers Views Company eMail

6-T XOR gate?

Intel,

4257

Differences between blocking and Non-blocking statements in Verilog?

Intel,

5 21051

Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?

IIT, Intel,

1 20819

Differences between functions and Procedures in VHDL?

Intel,

5 54997

What is component binding?

Intel,

2 6312

What is polymorphism? (C++)

Intel,

2 6080

What is hot electron effect?

Intel,

3 13381

Define threshold voltage?

College School Exams Tests, Intel, JHG, Wipro,

32 135295

Factors affecting Power Consumption on a chip?

Intel,

7 17362

Explain Clock Skew?

Intel, nvidia,

6 21636

Why do we use a Clock tree?

Intel,

3 13431

Explain the various Capacitances associated with a transistor and which one of them is the most prominent?

Intel,

2 8195

Explain the Various steps in Synthesis?

Intel,

3284

Explain ASIC Design Flow?

Intel, JK Associates, Mind Tree,

2 15444

Explain Custom Design Flow?

Intel,

2 7094

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Un-Answered Questions { VLSI }

What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

2898

Are you familiar with the term snooping?

3531

Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

1302

Explain the working of Insights of a pass gate ?

1242

Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

2843

Explain what is the use of defpararm?

1157

Explain depletion region.

1047

In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

1224

What is the difference between cmos and bipolar technologies?

1141

For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

1282

You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

1576

Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

1152

How about voltage source?

2277

What is Noise Margin? Explain the procedure to determine Noise Margin?

2466

Explain what is multiplexer?

1089

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