Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3871

What is Noise Margin? Explain the procedure to determine Noise Margin?

2466

What are the changes that are provided to meet design power targets?

1123

Implement a function with both ratioed and domino logic and merits and demerits of each logic?

3803

What is the ideal input and output resistance of a current source?

3016

You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

1576

Cross section of a PMOS transistor?

4777

What are the different design techniques required to create a layout for digital circuits?

1050

For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

1465

Are you familiar with the term snooping?

3532

What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

3273

What are the different classification of the timing control?

1119

Explain sizing of the inverter?

4437

If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?

2512

Mention what are three regions of operation of mosfet and how are they used?

1084