Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

718

Explain what is the depletion region?

622

In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

693

Are you familiar with the term MESI?

2115

Design an 8 is to 3 encoder using 4 is to encoder?

863

For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

942

What types of CMOS memories have you designed? What were their size? Speed?

2622

For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

710

Differences between Array and Booth Multipliers?

3537

How does Vbe and Ic change with temperature?

2951

What are the Advantages and disadvantages of Mealy and Moore?

702

What are the main issues associated with multiprocessor caches and how might you solve them?

1738

what is verilog?

634

What is the main function of metastability in vsdl?

601

Differences between IRSIM and SPICE?

4942