Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

859

Draw the stick diagram of a NOR gate. Optimize it

745

Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

805

What are the different design techniques required to create a layout for digital circuits?

588

Are you familiar with the term snooping?

2913

Explain Cross section of an NMOS transistor?

558

For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

702

what is verilog?

630

Explain the three regions of operation of a mosfet.

616

Give various factors on which threshold voltage depends.

742

What types of high speed CMOS circuits have you designed?

2052

What is the difference between nmos and pmos technologies?

636

For CMOS logic, give the various techniques you know to minimize power consumption

846

Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

2306

Explain sizing of the inverter?

3890