What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?
4 8696Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?
13 37499
Explain why is the number of gate inputs to cmos gates usually limited to four?
Explain about 6-T XOR gate?
Explain depletion region.
What types of CMOS memories have you designed? What were their size? Speed?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
What are the different design techniques required to create a layout for digital circuits?
Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
Explain the operation of a 6T-SRAM cell?
Implement a function with both ratioed and domino logic and merits and demerits of each logic?
Explain CMOS Inverter transfer characteristics?
What are the various regions of operation of mosfet? How are those regions used?
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
How binary number can give a signal or convert into a digital signal?
what is Slack?
what is the use of defpararm?