Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
632Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
897In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
682Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
692Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
718Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
686
Explain what is slack?
If not into production, how far did you follow the design and why did not you see it into production?
What are the different classification of the timing control?
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
Draw the SRAM Write Circuitry
Explain why present VLSI circuits use MOSFETs instead of BJTs?
What are the Advantages and disadvantages of Mealy and Moore?
What are the changes that are provided to meet design power targets?
6-T XOR gate?
Explain how Verilog is different to normal programming language?
Explain why is the number of gate inputs to cmos gates usually limited to four?
Explain the Charge Sharing problem while sampling data from a Bus?
What types of high speed CMOS circuits have you designed?
Explain the Working of a 2-stage OPAMP?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
