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Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)
6 13851Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
3 12530For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
2408Explain the operation considering a two processor computer system with a cache for each processor.
4740
Give various factors on which threshold voltage depends.
What are the main issues associated with multiprocessor caches and how might you solve them?
Why does the present vlsi circuits use mosfets instead of bjts?
How to improve these parameters? (Cascode topology, use long channel transistors)
Draw a CMOS Inverter. Explain its transfer characteristics
Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
Explain sizing of the inverter?
Implement a 2 I/P and gate using Tran gates?
what is SCR (Silicon Controlled Rectifier)?
What are the steps required to solve setup and hold violations in vlsi?
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
Explain Basic Stuff related to Perl?
Draw the stick diagram of a NOR gate. Optimize it
What are the different classification of the timing control?
In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
