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 Categories >> Software >> Embedded Systems >> VLSI
 
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verify nmos passes good logic 0 and passes bad logic 1.also verify that pmos passes good logic 1 and passes bad logic 0. hp   2  2157
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.    0  763
What is the mealy and moore machine's state diagram that can detect 3 consecutive heads of 3 coins ?    2  1603
what is the difference between the testing and verification? intel   0  1131
Need to convert this VHDL code into VLSI verilog code? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of specific package--- ENTITY tollbooth2 IS PORT (Clock,car_s,RE : IN STD_LOGIC; coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); r_light,g_light,alarm : OUT STD_LOGIC); END tollbooth2; ARCHITECTURE Behav OF tollbooth2 IS TYPE state_type IS (NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE D); ------GOTZERO = PAID $0.00--------- ------GOTFIV = PAID $0.05---------- ------GOTTEN = PAID $0.10---------- ------GOTFIF = PAID $0.15---------- ------GOTTWEN = PAID $0.20--------- SIGNAL present_state,next_state : state_type; BEGIN -----Next state is identified using present state,car & coin sensors------ PROCESS(present_state,car_s,coin_s) BEGIN CASE present_state IS WHEN NO_CAR => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= NO_CAR; END IF; WHEN GOTZERO => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTZERO; ELSIF (coin_s = "01") THEN next_state <= GOTFIV; ELSIF (coin_s ="10") THEN next_state <= GOTTEN; END IF; WHEN GOTFIV=> IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIV; ELSIF (coin_s = "01") THEN next_state <= GOTTEN; ELSIF (coin_s <= "10") THEN next_state <= GOTFIV; END IF; WHEN GOTTEN => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s ="00") THEN next_state <= GOTTEN; ELSIF (coin_s="01") THEN next_state <= GOTFIV; ELSIF (coin_s="10") THEN next_state <= GOTTWEN; END IF; WHEN GOTFIF => IF (car_s ='0') THEN next_state <= CHEATED; ELSIF (coin_s = "00") THEN next_state <= GOTFIF; ELSIF (coin_s ="01") THEN next_state <= GOTTWEN; ELSIF (coin_s = "10") THEN next_state <= GOTTWEN; END IF; WHEN GOTTWEN => next_state <= CAR_PAID; WHEN CAR_PAID => IF (car_s = '0') THEN next_state <= NO_CAR; ELSE next_state<= CAR_PAID; END IF; WHEN CHEATED => IF (car_s = '1') THEN next_state <= GOTZERO; ELSE next_state <= CHEATED; END IF; END CASE; END PROCESS;-----End of Process 1 -------PROCESS 2 for STATE REGISTER CLOCKING-------- PROCESS(Clock,RE) BEGIN IF RE = '1' THEN present_state <= GOTZERO; ----When the clock changes from low to high,the state of the system ----stored in next_state becomes the present state----- ELSIF Clock'EVENT AND Clock ='1' THEN present_state <= next_state; END IF; END PROCESS;-----End of Process 2------- --------------------------------------------------------- -----Conditional signal assignment statements---------- r_light <= '0' WHEN present_state = CAR_PAID ELSE '1'; g_light <= '1' WHEN present_state = CAR_PAID ELSE '0'; alarm <= '1' WHEN present_state = CHEATED ELSE '0'; END Behav;    0  1118
Write a VLSI program that implements a toll booth controller? patni   0  1438
WHAT IS THE DIFFERENCE BETWEEN TESTING AND VERIFICATION OF VLSI CIRCUIT? wipro   5  7399
What is the difference between fifo and the memory? intel   5  6216
What is the most complicated/valuable program you written in C/C++? intel   23  14793
If not into production, how far did you follow the design and why did not you see it into production? intel   1  1291
What was your role in the silicon evaluation/product ramp? What tools did you use? intel   0  844
What products have you designed which have entered high volume production? intel   1  2830
What transistor level design tools are you proficient with? What types of designs were they used on? intel   0  1430
What types of high speed CMOS circuits have you designed? intel   2  7601
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered? intel   0  731
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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45&#61549;m wide metal wire with sheet resistance R = 0.065 &#61527;/ and Cpermicron= 0.25 fF/&#61549;m. The resistance and capacitance of the unit NMOS are 6.5k&#61527; and 2.5fF. Use a 3 segment &#61552;-model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate. 763
How can you model a SRAM at RTL Level? 1706
Explain the operation of a 6T-SRAM cell? 1634
What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements? 293
Insights of a 2 input NOR gate. Explain the working? 622
If not into production, how far did you follow the design and why did not you see it into production? 319
Implement F= not (AB+CD) using CMOS gates? 834
What happens if we delay the enabling of Clock signal? 348
What types of CMOS memories have you designed? What were their size? Speed? 1491
How can you construct both PMOS and NMOS on a single substrate? 976
Explain the working of 4-bit Up/down Counter? 1445
What happens if we use an Inverter instead of the Differential Sense Amplifier? 409
If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics? 401
What was your role in the silicon evaluation/product ramp? What tools did you use? 844
Are you familiar with the term snooping? 461
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