How can you model a SRAM at RTL Level?

5740

What are the different design techniques required to create a layout for digital circuits?

1050

Explain the operation considering a two processor computer system with a cache for each processor.

2860

What transistor level design tools are you proficient with? What types of designs were they used on?

3448

What are the different gates where boolean logic are applicable?

1073

What is Noise Margin? Explain the procedure to determine Noise Margin?

2465

What are the main issues associated with multiprocessor caches and how might you solve them?

2242

Give various factors on which threshold voltage depends.

1311

How about voltage source?

2277

Explain how binary number can give a signal or convert into a digital signal?

1129

What is look up table in vlsi?

987

What are the different classification of the timing control?

1118

what is verilog?

1143

Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1616

Explain the working of 4-bit Up/down Counter?

4439