what is conductance and valence band?1 3036
What is Fermi level?5 4475
How does Vbe and Ic change with temperature?1694
If the substrate doping concentration increase, or temperature increases, how will Vt change? it increase or decrease?1104
what is Channel length modulation?1402
what is the doping?5 2982
What is the depletion region?1 2832
What are the two types of noise of MOSFET, how to eliminate them?(Thermal and Flicker).4 8302
What is the build-in potential?842
For a 0.18um and 0.8um technology MOSFET, which has a higher cutoff frequency?2 6328
How about voltage source?
If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
How can you model a SRAM at RTL Level?
Tell me how MOSFET works.
Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
If not into production, how far did you follow the design and why did not you see it into production?
How can you construct both PMOS and NMOS on a single substrate?
For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
Explain sizing of the inverter?
How does a Bandgap Voltage reference work?
Explain how MOSFET works?
What is Noise Margin? Explain the procedure to determine Noise Margin?
Basic Stuff related to Perl?
Insights of a 2 input NOR gate. Explain the working?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.