what is conductance and valence band?1 2773
What is Fermi level?5 4167
How does Vbe and Ic change with temperature?1630
If the substrate doping concentration increase, or temperature increases, how will Vt change? it increase or decrease?1064
what is Channel length modulation?1348
what is the doping?5 2736
What is the depletion region?1 2584
What are the two types of noise of MOSFET, how to eliminate them?(Thermal and Flicker).4 7983
What is the build-in potential?798
For a 0.18um and 0.8um technology MOSFET, which has a higher cutoff frequency?2 6027
Draw the Layout of an Inverter?
What is Body Effect?
For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
What products have you designed which have entered high volume production?
Explain the operation of a 6T-SRAM cell?
What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
Tell me the parameters as many as possible you know that used to character an amplifier?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
What happens if we delay the enabling of Clock signal?
If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
How does a Bandgap Voltage reference work?
What is the ideal input and output resistance of a current source?
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?