Answer / sharekhan

A region of width,W which is depleted of charge carriers
(ie electrons & holes) and containing only immobile ions
formed at the junction of n-type & p-type semiconductor.

For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

0 Answers   Intel,

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Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

0 Answers   Infosys,

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Advantages and disadvantages of Mealy and Moore?

2 Answers   Intel,

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How does a pn junction works?

2 Answers   Wipro,

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Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

0 Answers   Infosys,

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What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

0 Answers   Infosys,

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Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

0 Answers   Infosys,

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Are you familiar with the term MESI?

1 Answers   Intel,

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Explain the various MOSFET Capacitances & their significance ?

1 Answers   Infosys,

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What happens when the gate oxide is very thin?

3 Answers   Intel,

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How does Vbe and Ic change with temperature?

0 Answers   Qualcomm,

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What are the main issues associated with multiprocessor caches and how might you solve them?

1 Answers   Intel,

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