Why is Extraction performed?

1 Answers   Intel,

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Working of a 2-stage OPAMP?

0 Answers   Intel, Tata Elxsi,

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What are the total number of lines written by you in C/C++? What compiler was used?

1 Answers   Intel, Zensar,

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Why don?t we use just one NMOS or PMOS transistor as a transmission gate?

2 Answers   Infosys,

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Explain Custom Design Flow?

2 Answers   Intel,

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What is the difference between fifo and the memory?

6 Answers   DewSoft, Intel, Pentagon Rugged Systems,

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Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,

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What is the ideal input and output resistance of a current source?

0 Answers  

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Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

0 Answers   Infosys,

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Explain ASIC Design Flow?

2 Answers   Intel, JK Associates, Mind Tree,

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What is interrupt latency?

3 Answers  

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Insights of a 2 input NOR gate. Explain the working?

1 Answers   Infosys, Intel,

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