Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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How about voltage source?

0 Answers  

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Explain the usage of the shared SPI bus?

1 Answers  

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Write a VLSI program that implements a toll booth controller?

0 Answers   Patni,

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In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

0 Answers  

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what is body effect?

1 Answers  

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Insights of an inverter. Explain the working?

1 Answers   Intel,

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What is the most complicated/valuable program you written in C/C++?

23 Answers   HCL, IBM, Intel, TCS, TVS, Wipro,

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Have you studied buses? What types?

1 Answers   Intel,

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What are the steps required to solve setup and hold violations in vlsi?

0 Answers  

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Explain why is the number of gate inputs to cmos gates usually limited to four?

0 Answers  

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What are the changes that are provided to meet design power targets?

0 Answers  

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