Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

0 Answers   Infosys,

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What happens if we use an Inverter instead of the Differential Sense Amplifier?

0 Answers   Infosys,

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What is threshold voltage?

0 Answers  

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What is the mealy and moore machine's state diagram that can detect 3 consecutive heads of 3 coins ?

2 Answers  

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Mention what are three regions of operation of mosfet and how are they used?

0 Answers  

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What is component binding?

2 Answers   Intel,

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You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

4 Answers   Intel,

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What?s the difference between Testing & Verification?

6 Answers   Infosys,

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Explain the Various steps in Synthesis?

0 Answers   Intel,

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Give the expression for CMOS switching power dissipation?

2 Answers   Infosys,

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For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

3 Answers   Intel,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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