Have you studied buses? What types?

5 Answers   Intel,

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What is the function of chain reordering?

0 Answers  

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What are set up time & hold time constraints? What do they signify?

3 Answers  

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In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?

0 Answers  

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Draw the Layout of an Inverter?

0 Answers   Intel,

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Explain Cross section of a PMOS transistor?

0 Answers   Intel,

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In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

0 Answers   Infosys,

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Implement a function with both ratioed and domino logic and merits and demerits of each logic?

0 Answers   Intel,

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What is look up table in vlsi?

0 Answers  

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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Cross section of a PMOS transistor?

0 Answers   Intel,

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What is Noise Margin? Explain the procedure to determine Noise Margin?

4 Answers   Amkor, Cisco, Infosys, Intel,

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