what is charge sharing?

0 Answers   Intel,

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Advantages and disadvantages of Mealy and Moore?

2 Answers   Intel,

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What transistor level design tools are you proficient with? What types of designs were they used on?

0 Answers   Intel,

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What are the Advantages and disadvantages of Mealy and Moore?

0 Answers   Intel,

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What?s the critical path in a SRAM?

2 Answers   Infosys, Intel, Texas,

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.

0 Answers   Infosys,

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Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

0 Answers   Infosys,

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What is the difference between synchronous and asynchronous reset?

0 Answers  

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What was your role in the silicon evaluation or product ramp? What tools did you use?

0 Answers   Intel,

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How can you model a SRAM at RTL Level?

0 Answers   Infosys,

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Implement a 2 I/P and gate using Tran gates?

0 Answers   Intel,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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