Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

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What happens if we delay the enabling of Clock signal?

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What are the different classification of the timing control?

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You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

0 Answers   Infosys,

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Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,

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Write a pseudo code for sorting the numbers in an array?

2 Answers   Intel,

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what is the difference between the TTL chips and CMOS chips?

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What happens when the gate oxide is very thin?

3 Answers   Intel,

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What is hot electron effect?

3 Answers   Intel,

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Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

0 Answers   Infosys,

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What are the ways to Optimize the Performance of a Difference Amplifier?

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Tell me the parameters as many as possible you know that used to character an amplifier?

1 Answers  

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